Hi!
I am using VTune to measure the different levels of cache hits and misses (Load). I assumed L2_MISS = L3_HIT + L3_MISS (similarly for L1 and L2) but this does not seem to satisfy from the output below?
Config : Intel Core i3-5005u + Windows 10
CPU
Name: Intel(R) Core(TM) Processor code named Broadwell
Frequency: 2.0 GHz
Logical CPU Count: 4
Elapsed Time: 60.004s
CPU Time: 25.576s
CPI Rate: 1.641
Total Thread Count: 4
Paused Time: 0s
Hardware Events
Hardware Event Type Hardware Event Count Hardware Event Sample Count Events Per Sample
BACLEARS.ANY 223,106,693 97 100003
BR_MISP_RETIRED.ALL_BRANCHES_PS 64,401,449 7 400009
CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE 1,497,344,919 651 100003
CPU_CLK_UNHALTED.REF_TSC 51,034,000,000 25,517 2000000
CPU_CLK_UNHALTED.REF_XCLK 2,645,079,350 1,150 100003
CPU_CLK_UNHALTED.THREAD 51,314,000,000 25,657 2000000
CPU_CLK_UNHALTED.THREAD_P 47,242,070,863 1,027 2000003
CYCLE_ACTIVITY.STALLS_L1D_MISS 13,616,020,424 296 2000003
CYCLE_ACTIVITY.STALLS_L2_MISS 10,350,015,525 225 2000003
CYCLE_ACTIVITY.STALLS_MEM_ANY 20,332,030,498 442 2000003
CYCLE_ACTIVITY.STALLS_TOTAL 29,992,044,988 652 2000003
INST_RETIRED.ANY 31,262,000,000 15,631 2000000
INST_RETIRED.PREC_DIST 30,130,045,195 655 2000003
INST_RETIRED.X87 0 0 2000003
INT_MISC.RECOVERY_CYCLES 276,000,414 6 2000003
ITLB_MISSES.STLB_HIT 50,601,518 22 100003
ITLB_MISSES.WALK_COMPLETED 85,102,553 37 100003
ITLB_MISSES.WALK_DURATION 2,884,286,526 1,254 100003
L1D.REPLACEMENT 1,518,002,277 33 2000003
L1D_PEND_MISS.FB_FULL 46,000,069 1 2000003
L1D_PEND_MISS.PENDING 33,810,050,715 735 2000003
L2_RQSTS.RFO_HIT 55,200,828 12 200003
LD_BLOCKS.NO_SR 0 0 100003
LD_BLOCKS.STORE_FORWARD 39,101,173 17 100003
LD_BLOCKS_PARTIAL.ADDRESS_ALIAS 71,302,139 31 100003
LSD.CYCLES_4_UOPS 138,000,207 3 2000003
LSD.CYCLES_ACTIVE 92,000,138 2 2000003
LSD.UOPS 506,000,759 11 2000003
MACHINE_CLEARS.COUNT 2,300,069 1 100003
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM_PS 27,154,927 59 20011
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT_PS 10,585,819 23 20011
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS_PS 5,523,036 12 20011
MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS 565,816,974 246 100003
MEM_LOAD_UOPS_RETIRED.L1_HIT_PS 6,716,010,074 146 2000003
MEM_LOAD_UOPS_RETIRED.L1_MISS_PS 761,322,839 331 100003
MEM_LOAD_UOPS_RETIRED.L2_HIT_PS 434,713,041 189 100003
MEM_LOAD_UOPS_RETIRED.L2_MISS_PS 332,489,587 289 50021
MEM_LOAD_UOPS_RETIRED.L3_HIT_PS 287,620,750 250 50021
MEM_LOAD_UOPS_RETIRED.L3_MISS 9,200,644 4 100007
MEM_LOAD_UOPS_RETIRED.L3_MISS_PS 6,900,483 3 100007
MEM_UOPS_RETIRED.ALL_STORES_PS 5,888,008,832 128 2000003
MEM_UOPS_RETIRED.LOCK_LOADS_PS 262,218,354 114 100007
MEM_UOPS_RETIRED.SPLIT_LOADS_PS 4,600,138 2 100003
MEM_UOPS_RETIRED.SPLIT_STORES_PS 0 0 100003
MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS 108,103,243 47 100003
MEM_UOPS_RETIRED.STLB_MISS_STORES_PS 2,300,069 1 100003
Any help regarding this would be appreciated.
Thanks!